Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
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چکیده
This study presents a proposal to estimate the power consumption of the complex logic gate with topology dogbone transistors, which reduces the effects of radiation, by of the estimate of input and output capacitance of gate. The simulation tools have been implementation and SIS and comparator with the Hspice Synopsys. The first results show approximately an error of 5% between the proposed and simulated method.
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تاریخ انتشار 2009